The present invention relates to the design of integrated circuit electrostatic discharge protection (ESD) devices.
Integrated circuits have evolved into ever increasing higher circuit densities, with a corresponding reduction in size of circuit elements. The progress of integrated circuit technology has advanced to the point where active FET (Field Effect transistors) devices have gate lengths which are in the tenths of a micrometer. The integrated circuits have external connection pins which are vulnerable to ESD events due to handling by individuals who work with these package devices, and the thinner gates are susceptible to destruction from electrostatic discharge (ESD).
ESD protection has developed to the point where there are various models representing these events. Specifically, a human body model (HBM) has been developed which represents the discharge between two pins on an integrated circuit from the electrostatic potential on a human body. Typically, tests are conducted between all pins of the integrated circuit using the human body model.
A machine model (MM) has also been developed to represent the discharge from a machine tool which may have been charged with an electrostatic potential to an integrated circuit pin, and the peak current from this model can be as high as five amperes.
Efforts have been made to incorporate circuitry within the integrated circuit which will suppress the discharge resulting from an ESD event to a level which will not harm any of the devices which may be connected to an external pin of the circuit.
It is common in integrated circuit design to include ESD protection to the terminals which receive an operating voltage for the device. In this event, a sudden surge in voltage from an ESD event can be safely discharged so that no damage results to the internal active devices of the integrated circuit. The clamping circuits which hold the voltage across the power supply terminals to the nominal power supply voltage often require a large FET capable of discharging current which is produced from an ESD event which, however brief, may result in a peak current of two-three amperes or more and a peak voltage of many thousands of volts.
When an ESD potential occurs across the power supply terminals the large FET transistor conducts clamping the power supply terminal voltage. The large FET transistor is biased on when the inverter circuit connected to the gate of the large FET transistor switches to a level to render the device conducting to rapidly discharge the ESD event. Once the ESD event is discharged, an RC timing circuit, also connected to the power supply terminals, produces a timing signal. The inverter is connected between the timing circuit and the gate connection of the large FET transistor further delaying the timing signal produced from the RC timing circuit. The delayed timing signal biases the large FET clamping transistor off.
In developing these devices, the prior art used feedback to the inverter to increase the time delay, permitting the capacitor and resistor sizes for the RC timing circuit to be reduced. In this way, the circuit size can be reduced since a smaller capacitor and resistor may be used in the timing circuit.
These techniques, however, have not fully addressed the problems with power supply clamping circuits which suppress the ESD event. Specifically, the power clamp can be mistriggered by a voltage spike on the power supply, or, when the power supply is first powered up, the voltage may briefly rise to a level which will trigger the ESD protection. The power clamp can then only be reset by recycling the power supply.
Accordingly, there is the need to provide a power clamp circuit less susceptible to mistriggering and which will automatically reset if a mistrigger event does occur.